Selected publications

  1. Cryo-CMOS Circuits and Systems for Quantum Computing Applications
    Bishnu Patra; Rosario M. Incandela; Jeroen P. G. van Dijk; Harald A. R. Homulle; Lin Song; Mina Shahmohammadi; Robert B. Staszewski; Andrei Vladimirescu; Masoud Babaie; Fabio Sebastiano; Edoardo Charbon;
    IEEE Journal of Solid-State Circuits,
    Volume 53, Issue 1, pp. 1-13, Jan 2018. DOI: 10.1109/JSSC.2017.2737549
    Keywords: CMOS technology;Cryogenics;Oscillators;Process control;Quantum computing;Temperature;CMOS characterization;Class-F oscillator;cryo-CMOS;low-noise amplifier (LNA);noise canceling;phase noise (PN);quantum bit (qubit);quantum computing;qubit control;single-photon avalanche diode (SPAD)..
    Abstract: ...
    A fault-tolerant quantum computer with millions of quantum bits (qubits) requires massive yet very precise control electronics for the manipulation and readout of individual qubits. CMOS operating at cryogenic temperatures down to 4 K (cryo-CMOS) allows for closer system integration, thus promising a scalable solution to enable future quantum computers. In this paper, a cryogenic control system is proposed, along with the required specifications, for the interface of the classical electronics with the quantum processor. To prove the advantages of such a system, the functionality of key circuit blocks is experimentally demonstrated. The characteristic properties of cryo-CMOS are exploited to design a noise-canceling low-noise amplifier for spin-qubit RF-reflectometry readout and a class-F2,3 digitally controlled oscillator required to manipulate the state of qubits.

  2. A Dynamic Zoom ADC with 109-dB DR for Audio Applications
    B. Gonen; F. Sebastiano; K. Makinwa;
    IEEE Journal of Solid-State Circuits,
    Volume 52, pp. 1542-1550, 6 2017.
    Abstract: ...
    This paper presents the first dynamic zoom ADC. Intended for audio applications, it achieves 109-dB DR, 106-dB signal-to-noise ratio, and 103-dB SNDR in a 20-kHz bandwidth, while dissipating only 1.12 mW. This translates into the state-of-the-art energy efficiency as expressed by a Schreier FoM of 181.5 dB. It also achieves the state-of-the-art area efficiency, occupying only 0.16 mm2 in the 0.16- μm CMOS. These advances are enabled by the use of concurrent fine and coarse conversions, dynamic error-correction techniques, and a dynamically biased inverter-based operational transconductance amplifier.

  3. Analysis and Design of VCO-Based Phase-Domain ΣΔ Modulators
    U. Sonmez; F. Sebastiano; K. Makinwa;
    IEEE Transactions on Circuits and Systems I,
    Volume 64, pp. 1075-1084, 5 2017.
    Abstract: ...
    VCO-based phase-domain ΣΔ modulators employ the combination of a voltage-controlled-oscillator (VCO) and an up/down counter to replace the analog loop filter used in conventional ΣΔ modulators. Thanks to this highly digital architecture, they can be quite compact, and are expected to shrink even further with CMOS scaling. This paper describes the analysis and design of such converters. Trade-offs between design parameters and the impact of non-idealities, such as finite counter length and VCO non-linearity, are assessed through both theoretical analysis and behavioral simulations. The proposed design methodology is applied to the design of a phase-to-digital converter in a 40-nm CMOS process, which is used to digitize the output of a thermal-diffusivity temperature sensor, achieving ± 0.2° (3σ) phase inaccuracy from -40 to 125 °C and a sensor-limited resolution of 57 m° (RMS) within a 500-Hz bandwidth. Measurements on the prototype agree quite well with theoretical predictions, thus demonstrating the validity of the proposed design methodology.

  4. A Compact Thermal-Diffusivity-Based Temperature Sensors in 40-nm CMOS for SoC Thermal Monitoring
    U. Sonmez; F. Sebastiano; K. Makinwa;
    IEEE Journal of Solid-State Circuits,
    Volume 52, Issue 3, pp. 834-843, March 2017.

  5. A Dynamic Zoom ADC With 109-dB DR for Audio Applications
    Burak Gönen; Fabio Sebastiano; Rui Quan; Robert van Veldhoven; Kofi A.A. Makinwa;
    IEEE Journal of Solid-State Circuits,
    Volume 52, Issue 6, pp. 1542-1550, June 2017. DOI: 10.1109/JSSC.2017.2669022
    Keywords: CMOS integrated circuits;analogue-digital conversion;audio signal processing;error correction;invertors;operational amplifiers;CMOS;Schreier FoM;area efficiency;audio applications;bandwidth 20 kHz;coarse conversions;concurrent fine conversions;dynamic error-correction techniques;dynamic zoom ADC;dynamically biased inverter;energy efficiency;operational transconductance amplifier;power 1.12 mW;signal-to-noiseratio;size 0.16 mum;Bandwidth;Dynamic range;Linearity;Quantization (signal);Signal resolution;Signal to noise ratio;Vehicle dynamics;Audio;compact ADC;delta sigma;discrete time;dynamic;dynamic range (DR);hybrid ADC;precision;zoom ADC.
    Abstract: ...
    This paper presents the first dynamic zoom ADC. Intended for audio applications, it achieves 109-dB DR, 106-dB signal-to-noise ratio, and 103-dB SNDR in a 20-kHz bandwidth, while dissipating only 1.12 mW. This translates into the state-of-the-art energy efficiency as expressed by a Schreier FoM of 181.5 dB. It also achieves the state-of-the-art area efficiency, occupying only 0.16 mm² in the 0.16-µm CMOS. These advances are enabled by the use of concurrent fine and coarse conversions, dynamic error-correction techniques, and a dynamically biased inverter-based operational transconductance amplifier.

  6. Compact Thermal-Diffusivity-Based Temperature Sensors in 40-nm CMOS for SoC Thermal Monitoring
    U. Sonmez; F. Sebastiano; K.A.A. Makinwa;
    IEEE Journal of Solid-State Circuits,
    Volume 52, Issue 3, pp. 8, 3 2017.
    Abstract: ...
    An array of temperature sensors based on the thermal diffusivity (TD) of bulk silicon has been realized in a standard 40-nm CMOS process. In each TD sensor, a highly digital voltage-controlled oscillator-based ΣΔ ADC digitizes the temperature-dependent phase shift of an electrothermal filter (ETF). A phase calibration scheme is used to cancel the ADC's phase offset. Two types of ETF were realized, one optimized for accuracy and one optimized for resolution. Sensors based on the accuracy-optimized ETF achieved a resolution of 0.36 °C (rms) at 1 kSa/s, and inaccuracies of ±1.4 °C (3σ, uncalibrated) and ±0.75 °C (3σ, room-temperature calibrated) from -40 °C to 125 °C. Sensors based on the resolution-optimized ETFs achieved an improved resolution of 0.21 °C (rms), and inaccuracies of ±2.3 °C (3σ, uncalibrated) and ±1.05 °C (3σ, room-temperature calibrated). The sensors draw 2.8 mA from supply voltages as low as 0.9 V, and occupy only 1650 μm2, making them some of the smallest smart temperature sensors reported to date, and well suited for thermal monitoring applications in systems-on-chip.

  7. Analysis and Design of VCO-Based Phase-Domain $\Sigma \Delta $ Modulators
    Ugur Sönmez; Fabio Sebastiano; Kofi A. A. Makinwa;
    IEEE Transactions on Circuits and Systems I: Regular Papers,
    Volume 64, Issue 5, pp. 1075-1084, May 2017. DOI: 10.1109/TCSI.2016.2638827
    Keywords: CMOS digital integrated circuits;sigma-delta modulation;voltage-controlled oscillators;CMOS process;CMOS scaling;VCO nonlinearity;VCO-based phase-domain S? modulators;analog loop filter;bandwidth 500 Hz;finite counter length;phase-to-digital converter;size 40 nm;temperature -40 C to 125 C;thermal-diffusivity temperature sensor;up-down counter;voltage-controlled-oscillator;Phase modulation;Quantization (signal);Radiation detectors;Temperature sensors;Voltage-controlled oscillators;Phase-to-digital converter;VCO-based sigma-delta modulator;quantization noise;time-to-digital converter.
    Abstract: ...
    VCO-based phase-domain $\Sigma\Delta$ modulators employ the combination of a voltage-controlled-oscillator (VCO) and an up/down counter to replace the analog loop filter used in conventional $\Sigma\Delta$ modulators. Thanks to this highly digital architecture, they can be quite compact, and are expected to shrink even further with CMOS scaling. This paper describes the analysis and design of such converters. Trade-offs between design parameters and the impact of non-idealities, such as finite counter length and VCO non-linearity, are assessed through both theoretical analysis and behavioral simulations. The proposed design methodology is applied to the design of a phase-to-digital converter in a 40-nm CMOS process, which is used to digitize the output of a thermal-diffusivity temperature sensor, achieving 0.2° (3σ) phase inaccuracy from -40 to 125 °C and a sensor-limited resolution of 57 m$\Sigma\Delta$ (RMS) within a 500-Hz bandwidth. Measurements on the prototype agree quite well with theoretical predictions, thus demonstrating the validity of the proposed design methodology.

  8. Quantum information density scaling and qubit operation time constraints of CMOS silicon-based quantum computer architectures
    Davide Rotta; Fabio Sebastiano; Edoardo Charbon; Enrico Prati;
    npj Quantum Information,
    Volume 3, Issue 1, pp. 26, 2017. DOI: 10.1038/s41534-017-0023-5
    Abstract: ...
    Even the quantum simulation of an apparently simple molecule such as Fe2S2 requires a considerable number of qubits of the order of 106, while more complex molecules such as alanine (C3H7NO2) require about a hundred times more. In order to assess such a multimillion scale of identical qubits and control lines, the silicon platform seems to be one of the most indicated routes as it naturally provides, together with qubit functionalities, the capability of nanometric, serial, and industrial-quality fabrication. The scaling trend of microelectronic devices predicting that computing power would double every 2 years, known as Moores law, according to the new slope set after the 32-nm node of 2009, suggests that the technology roadmap will achieve the 3-nm manufacturability limit proposed by Kelly around 2020. Today, circuital quantum information processing architectures are predicted to take advantage from the scalability ensured by silicon technology. However, the maximum amount of quantum information per unit surface that can be stored in silicon-based qubits and the consequent space constraints on qubit operations have never been addressed so far. This represents one of the key parameters toward the implementation of quantum error correction for fault-tolerant quantum information processing and its dependence on the features of the technology node. The maximum quantum information per unit surface virtually storable and controllable in the compact exchange-only silicon double quantum dot qubit architecture is expressed as a function of the complementary metaloxidesemiconductor technology node, so the size scale optimizing both physical qubit operation time and quantum error correction requirements is assessed by reviewing the physical and technological constraints. According to the requirements imposed by the quantum error correction method and the constraints given by the typical strength of the exchange coupling, we determine the workable operation frequency range of a silicon complementary metaloxidesemiconductor quantum processor to be within 1 and 100?GHz. Such constraint limits the feasibility of fault-tolerant quantum information processing with complementary metaloxidesemiconductor technology only to the most advanced nodes. The compatibility with classical complementary metaloxidesemiconductor control circuitry is discussed, focusing on the cryogenic complementary metaloxidesemiconductor operation required to bring the classical controller as close as possible to the quantum processor and to enable interfacing thousands of qubits on the same chip via time-division, frequency-division, and space-division multiplexing. The operation time range prospected for cryogenic control electronics is found to be compatible with the operation time expected for qubits. By combining the forecast of the development of scaled technology nodes with operation time and classical circuitry constraints, we derive a maximum quantum information density for logical qubits of 2.8 and 4?Mqb/cm2 for the 10 and 7-nm technology nodes, respectively, for the Steane code. The density is one and two orders of magnitude less for surface codes and for concatenated codes, respectively. Such values provide a benchmark for the development of fault-tolerant quantum algorithms by circuital quantum information based on silicon platforms and a guideline for other technologies in general.

    document

  9. A reconfigurable cryogenic platform for the classical control of quantum processors
    Harald Homulle; Stefan Visser; Bishnu Patra; Giorgio Ferrari; Enrico Prati; Fabio Sebastiano; Edoardo Charbon; Enrico Prati;
    Review of Scientific Instruments,
    Volume 88, Issue 4, pp. 045103, 2017. DOI: 10.1063/1.4979611
    Abstract: ...
    The implementation of a classical control infrastructure for large-scale quantum computers is challenging due to the need for integration and processing time, which is constrained by coherence time. We propose a cryogenic reconfigurable platform as the heart of the control infrastructure implementing the digital error-correction control loop. The platform is implemented on a field-programmable gate array (FPGA) that supports the functionality required by several qubit technologies and that can operate close to the physical qubits over a temperature range from 4 K to 300 K. This work focuses on the extensive characterization of the electronic platform over this temperature range. All major FPGA building blocks (such as look-up tables (LUTs), carry chains (CARRY4), mixed-mode clock manager (MMCM), phase-locked loop (PLL), block random access memory, and IDELAY2 (programmable delay element)) operate correctly and the logic speed is very stable. The logic speed of LUTs and CARRY4 changes less then 5%, whereas the jitter of MMCM and PLL clock managers is reduced by 20%. The stability is finally demonstrated by operating an integrated 1.2 GSa/s analog-to-digital converter (ADC) with a relatively stable performance over temperature. The ADCs effective number of bits drops from 6 to 4.5 bits when operating at 15 K.} url={https://doi.org/10.1063/1.4979611

  10. A Hybrid ADC for High Resolution: The Zoom ADC
    B. Gönen; F. Sebastiano; R. van Veldhoven; K.A.A. Makinwa;
    Springer, , 2017.

  11. A Hybrid ADC for High Resolution: The Zoom ADC
    B. Gönen; F. Sebastiano; R. van Veldhoven; K.A.A. Makinwa;
    In Proc. Advances in Analog Circuit Design Workshop (AACD),
    April 2017.

  12. A Frequency-Locked Loop Based on an Oxide Electrothermal Filter in Standard CMOS
    L. Pedala; C. Gurleyuk; S. Pan; F. Sebastiano; K. Makinwa;
    In European Solid-State Circuits Conference (ESSCIRC),
    Leuven, Belgium, 9 2017.

  13. Cryo-CMOS circuits and systems for scalable quantum computing
    Edoardo Charbon; Fabio Sebastiano; Masoud Babaie; Andrei Vladimirescu; Mina Shahmohammadi; R. B. Staszewski; Harald A. R. Homulle; Bishnu Patra; Jeroen P. G. van Dijk; Rosario M. Incandela; Lin Song; Bahador Valizadehpasha;
    In 2017 IEEE International Solid-State Circuits Conference (ISSCC),
    pp. 264-265, Feb 2017. DOI: 10.1109/ISSCC.2017.7870362
    Keywords: CMOS integrated circuits;logic circuits;quantum computing;cryo-CMOS circuits;error-correcting loop;quantum algorithm;quantum bits arrays;quantum coherence loss;qubit states;room-temperature controller;scalable quantum computing;state-of-the-art quantum processors;unprecedented computation power;Cryogenics;Oscillators;Program processors;Quantum computing;Semiconductor device modeling;Substrates;Temperature sensors.
    Abstract: ...
    In Paper 15.5, Delft University of Technology, EPFL, and Intel present building blocks for a scalable CMOS interface to solid-state quantum processors with a projected efficiency of 200W/qubit. The circuits include an analog noise-canceled 1.2GHz LNA with 28dB gain, a 6.2GHz class-F local oscillator with better than 145dBc/Hz phase noise at 10MHz offset, a 12µm SPAD with 0.1Hz dark count rate at 2V excess bias, and digital logic, all designed using ad hoc deep-cryogenic models.

  14. A hybrid ADC for high resolution: the Zoom ADC
    Burak Gönen; Fabio Sebastiano; Robert H. M. van Veldhoven Kofi A. A. Makinwa;
    In Proc. Workshop on Advances in Analog Circuit Design (AACD),
    Eindhoven, The Netherlands, March 2017. DOI: 10.1109/IWASI.2017.7974215

  15. Cryogenic CMOS interfaces for quantum devices
    Fabio Sebastiano; Harald A. R. Homulle; Jeroen P. G. van Dijk; Rosario M. Incandela; Bishnu Patra; M. Mehrpoo; Masoud Babaie; Andrei Vladimirescu; Edoardo Charbon;
    In 2017 7th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI),
    Vieste, Italy, pp. 59-62, June 2017. DOI: 10.1109/IWASI.2017.7974215
    Keywords: CMOS technology;Computers;Cryogenics;Process control;Quantum computing;Semiconductor device modeling;Standards;CMOS;cryo-CMOS;cryogenics;quantum computing;qubits.
    Abstract: ...
    Quantum computers could efficiently solve problems that are intractable by today's computers, thus offering the possibility to radically change entire industries and revolutionize our lives. A quantum computer comprises a quantum processor operating at cryogenic temperature and an electronic interface for its control, which is currently implemented at room temperature for the few qubits available today. However, this approach becomes impractical as the number of qubits grows towards the tens of thousands required for complex quantum algorithms with practical applications. We propose an electronic interface for sensing and controlling qubits operating at cryogenic temperature implemented in standard CMOS.

  16. Cryo-CMOS Electronic Control for Scalable Quantum Computing: Invited
    Fabio Sebastiano; Harald Homulle; Bishnu Patra; Rosario Incandela; Jeroen van Dijk; Lin Song; Masoud Babaie; Andrei Vladimirescu; Edoardo Charbon;
    In Proceedings of the 54th Annual Design Automation Conference 2017,
    New York, NY, USA, ACM, pp. 13:1--13:6, 2017. DOI: 10.1145/3061639.3072948
    Keywords: Cryo-CMOS, cryogenics, device models, error-correcting loop, quantum computation, qubit.
    document

  17. Sensor system with a full bridge configuration of four resistive sensing elements
    Edwin Schapendonk, Piet van der Zee; Fabio Sebastiano; Robert H.M. van Veldhoven;
    Patent, Europe 2955492 B1, May 2017.

  18. Driver for switched-capacitor circuits
    Fabio Sebastiano;
    Patent, united States 9614519 B2, April 2017.

  19. Tunable single hole regime of a silicon field effect transistor in standard CMOS technolog
    Marco Turchetti; Harald Homulle; Fabio Sebastiano; Giorgio Ferrari; Edoardo Charbon; Enrico Prati;
    Applied Physics Express,
    Volume 9, Issue 1, pp. 014001, 2016. DOI: 10.7567/APEX.9.014001
    Abstract: ...
    The electrical properties of a Single Hole Field Effect Transistor (SH-FET) based on CMOS technology are analyzed in a cryogenic environment. Few electron?hole Coulomb diamonds are observed using quantum transport spectroscopy measurements, down to the limit of single hole transport. Controlling the hole filling of the SH-FET is made possible by biasing the top gate, while the bulk contact is employed as a back gate that tunes the hole state coupling with the contacts and their distance from the interface. We compare the cryogenic Coulomb blockade regime with the room temperature regime, where the device operation is similar to that of a standard p-MOSFET.

    document

  20. Cryo-CMOS for Quantum Computing
    E. Charbon; F. Sebastiano; A. Vladimirescu; H. Homulle; S. Visser; L. Song; R. Incandela;
    In Internation Electon Devices Meeting (IEDM),
    December 2016.

  21. An Oxide Electrothermal Filter in Standard CMOS
    L. Pedalà; U. Sönmez; F. Sebastiano; K.A.A. Makinwa; K. Nagaraj; J. Park;
    In 2016 IEEE Sensors,
    Orlando, FL, USA, pp. 343-345, November 2016.

  22. Characterization of bipolar transistors for cryogenic temperature sensors in standard CMOS
    L. Song; H. Homulle; E. Charbon; F. Sebastiano;
    In IEEE Sensors 2016,
    October 2016.

  23. A 1.65mW 0.16mm² Dynamic Zoom-ADC with 107.5dB DR in 20kHz BW
    B. Gönen; F. Sebastiano; van R. Veldhoven; K.A.A. Makinwa;
    In 2016 IEEE International Solid-State Circuits Conference (ISSCC),
    IEEE, pp. 282-283, Feb 2016.

  24. 1650µm² Thermal-Diffusivity Sensors with Inaccuracies Down to ±0.75°C in 40nm CMOS
    U. Sonmez; F. Sebastiano; K.A.A. Makinwa;
    In 2016 IEEE International Solid-State Circuits Conference (ISSCC),
    IEEE, pp. 206-207, Feb 2016.

  25. 1650µm² Thermal-Diffusivity Sensors with Inaccuracies Down to ±0.75$^\circ$C in 40nm CMOS
    Ugur Sönmez; Fabio Sebastiano; Kofi A.A. Makinwa;
    In International Solid-state Circuits Conference Digest of Technical Papers,
    San Francisco, CA, pp. 206-207, Jan 2016. DOI: 10.1109/ISSCC.2016.7417979
    Keywords: CMOS integrated circuits;calibration;delta-sigma modulation;temperature sensors;thermal diffusivity;CMOS;digital phase-domain ?S ADC;phase-calibration scheme;scaling;single-point trim;size 40 nm;smart temperature sensors;temperature -40 degC to 125 degC;thermal monitoring;thermal-diffusivity sensors;CMOS integrated circuits;Monitoring;Radiation detectors;Temperature measurement;Temperature sensors.
    Abstract: ...
    This work presents a thermal diffusivity (TD) sensor realized in nanometer (40nm) CMOS that demonstrates that the performance of such sensors continues to improve with scaling. Without trimming, the sensor achieves 1.4C (3s) inaccuracy from -40 to 125C, which is a 5 improvement over previous (non-TD) sensors intended for thermal monitoring. This improves to 0.75C (3s) after a single-point trim, a level of accuracy that previously would have required two-point trimming. Furthermore, it operates from supply voltages as low as 0.9V, and occupies only 1650 m2, making it one of the smallest smart temperature sensors reported to date. These advances are enabled by the use of a phase-calibration scheme and a highly digital phase-domain ?S ADC.

  26. A 1.65mW 0.16mm² Dynamic Zoom-ADC with 107.5dB DR in 20kHz BW
    Burak Gönen; Fabio Sebastiano; and Robert.van Veldhoven; Kofi A.A. Makinwa;
    In International Solid-state Circuits Conference Digest of Technical Papers,
    San Francisco, CA, pp. 282-283, Jan 2016. DOI: 10.1109/ISSCC.2016.7418017
    Keywords: codecs;delta-sigma modulation;energy conservation;error correction;invertors;operational amplifiers;SNR;acoustic noise;audio codec;automotive application;bandwidth 20 kHz;dynamic zoom-ADC;echo cancellation;energy-efficient SAR ADC;error-correction technique;inverter-based OTA;low-distortion ?S ADC;operational transconductance amplifier;power 1.65 mW;quasistatic signal;signal-noise ratio;smartphone;stereo channel;successive approximation register analog-digital converter;Bandwidth;Capacitors;Energy efficiency;Linearity;Modulation;Solid state circuits;Vehicle dynamics.
    Abstract: ...
    Audio codecs for automotive applications and smartphones require up to five stereo channels to achieve effective acoustic noise and echo cancellation, thus demanding ADCs with low power and minimal die area. Zoom-ADCs should be well suited for such applications, since they combine compact and energy-efficient SAR ADCs with low-distortion ?S ADCs to simultaneously achieve high energy efficiency, small die area, and high linearity [1,2]. However, previous implementations were limited to the conversion of quasi-static signals, since the two ADCs were operated sequentially, with a coarse SAR conversion followed by, a much slower, fine ?S conversion. This work describes a zoom-ADC with a 20kHz bandwidth, which achieves 107.5dB DR and 104.4dB SNR while dissipating 1.65mW and occupying 0.16mm2. A comparison with recent state-of-the-art ADCs with similar resolution and bandwidth [3-7] shows that the ADC achieves significantly improved energy and area efficiency. These advances are enabled by the use of concurrent fine and coarse conversions, dynamic error-correction techniques, and an inverter-based OTA.

  27. CryoCMOS Hardware Technology a Classical Infrastructure for a Scalable Quantum Computer
    Harald Homulle; Stefan Visser; Bishnu Patra; Giorgio Ferrari; Enrico Prati; Carmen G. Almud{\'e}ver; Koen Bertels; Fabio Sebastiano; Edoardo Charbon;
    In Proceedings of the ACM International Conference on Computing Frontiers,
    New York, NY, USA, ACM, pp. 282--287, 2016. DOI: 10.1145/2903150.2906828
    Keywords: (de)coherence, CryoCMOS, cryogenics, error-correcting loop, fault-tolerant computing, quantum computation, quantum micro-architecture, qubit.
    Abstract: ...
    We propose a classical infrastructure for a quantum computer implemented in CMOS. The peculiarity of the approach is to operate the classical CMOS circuits and systems at deep cryogenic temperatures (cryoCMOS), so as to ensure physical proximity to the quantum bits, thus reducing thermal gradients and increasing compactness. CryoCMOS technology leverages the CMOS fabrication infrastructure and exploits the continuous effort of miniaturization that has sustained Moores Law for over 50 years. Such approach is believed to enable the growth of the number of qubits operating in a fault-tolerant fashion, paving the way to scalable quantum computing machines.

    document

  28. A Heterogeneous Quantum Computer Architecture
    X. Fu; L. Riesebos; L. Lao; C.G. Almudever; F. Sebastiano; R. Versluis; E. Charbon; K. Bertels;
    In Proceedings of the ACM International Conference on Computing Frontiers,
    New York, NY, USA, ACM, pp. 323--330, 2016. DOI: 10.1145/2903150.2906827
    Abstract: ...
    In this paper, we present a high level view of the heterogeneous quantum computer architecture as any future quantum computer will consist of both a classical and quantum computing part. The classical part is needed for error correction as well as for the execution of algorithms that contain both classical and quantum logic. We present a complete system stack describing the di?erent layers when building a quantum computer. We also present the control logic and corresponding data path that needs to be implemented when executing quantum instructions and conclude by discussing design choices in the quantum plane.} keywords = {quantum computer (micro-)architecture

    document

  29. Characterization of bipolar transistors for cryogenic temperature sensors in standard CMOS
    Lin Song; Harald Homulle; Edoardo Charbon; Fabio Sebastiano;
    In IEEE Sensors 2016,
    pp. 1-3, October 2016. DOI: 10.1109/ICSENS.2016.7808759
    Keywords: CMOS integrated circuits;bipolar transistors;cryogenics;temperature sensors;CMOS integrated temperature sensors;bipolar substrate PNP;bipolar transistors;carrier freeze-out;cryogenic temperature sensors;finite current gain;parasitic base resistance;size 160 nm;standard CMOS;temperature 7 K to 298 K;CMOS technology;Cryogenics;Standards;Substrates;Temperature distribution;Temperature sensors;CMOS;cryogenics;substrate bipolar transistors;temperature sensors.
    Abstract: ...
    This paper presents the cryogenic characterization of the bipolar substrate PNPs that are typically employed as sensing elements in CMOS integrated temperature sensors. PNPs realized in a standard 160-nm CMOS technology were characterized over the temperature range from 7 K to 294 K. Although PNP non-idealities, such as finite current gain and parasitic base resistance, deteriorate at lower temperature, device operation similar to room temperature is observed down to 70 K, while operation at lower temperatures is limited by carrier freeze-out in the base region and limited current gain. These results demonstrate the feasibility of temperature sensors in standard CMOS at cryogenic temperature.

  30. An Oxide Electrothermal Filter in Standard CMOS
    Lorenzo Pedal\'{a}; Ugur Sönmez; Fabio Sebastiano; K ofi A.A. Makinwa; K. Nagaraj; J. Park;
    In 2016 IEEE Sensors,
    IEEE} abstract={Due to their relatively stable phase shift over temperature, electrothermal filters (ETFs) with an oxide heat path have been used as on-chip phase references, e.g. for thermal diffusivity (TD) temperature sensors. However, previous oxide E, Oct 2016. DOI: 10.1109/ICSENS.2016.7808512
    Keywords: CMOS integrated circuits;elemental semiconductors;silicon;silicon-on-insulator;temperature measurement;temperature sensors;ETF;SOI processing;Si;TD temperature sensor;bulk standard CMOS process;deep-trench isolation;on-chip phase reference;oxide electrothermal filter;oxide-dominated heat path;temperature -40 degC to 125 degC;thermal diffusivity temperature sensor;Decision support systems;Electronic mail;Heating;Standards;System-on-chip;Temperature sensors;electrothermal filter;phase domain sigma delta ADC;self-referenced;temperature sensor;thermal diffusivity.

  31. Cryo-CMOS for quantum computing
    Edoardo Charbon; Fabio Sebastiano; Andrei Vladimirescu; Harald Homulle; Stefan Visser; Lin Song; Rosario M. Incandela;
    In Proc. 2016 IEEE International Electron Devices Meeting (IEDM),
    pp. 13.5.1-13.5.4, Dec 2016. DOI: 10.1109/IEDM.2016.7838410
    Keywords: CMOS integrated circuits;VLSI;cryogenic electronics;fault tolerance;integrated circuit design;integrated circuit reliability;quantum computing;VLSI design;cryoCMOS;cryogenic CMOS circuits;cryogenic CMOS systems;deep-cryogenic temperatures;fault-tolerant quantum bits;fault-tolerant qubit system;quantum computing;Computers;Fault tolerance;Fault tolerant systems;Field programmable gate arrays;Multiplexing;Quantum computing;Quantum dots.
    Abstract: ...
    Cryogenic CMOS, or cryo-CMOS circuits and systems, are emerging in VLSI design for many applications, in primis quantum computing. Fault-tolerant quantum bits (qubits) in surface code configurations, one of the most accepted implementations in quantum computing, operate in deep sub-Kelvin regime and require scalable classical control circuits. In this paper we advocate the need for a new generation of deep-submicron CMOS circuits operating at deep-cryogenic temperatures to achieve the performance required in a fault-tolerant qubit system. We outline the challenges and limitations of operating CMOS in near-zero Kelvin regimes and we propose solutions. The paper concludes with several examples showing the suitability of integrating fault-tolerant.qubits with CMOS.

  32. Efficient Analog to Digital Converter
    B. Gönen; F. Sebastiano; K.A.A. Makinwa; R.H.M. van Veldhoven;
    Patent, 9,325,340, April 26 2016.

  33. Frequency synthesiser
    Salvatore Drago; Fabio Sebastiano; Domine M.W. Leenaerts; Lucien J. Breems; Bram Nauta;
    Patent, United States 9240772 B2, January 2016.

  34. Efficient analog to digital converter
    Burak Gönen; Fabio Sebastiano; Kofi A. A. Makinwa; Robert H. M. van Veldhoven;
    Patent, Europe 9325340, April 2016.

  35. A 2800-µm² Thermal-Diffusivity Temperature Sensor with VCO-Based Readout in 160-nm CMOS
    Jan Angevare; Lorenzo Pedalà; Ugur Sonmez; Fabio Sebastiano; Kofi A.A. Makinwa;
    In Asian Solid-state Circuits Conference Digest of Technical Papers,
    Xiamen, China, pp. 1-4, Nov 2015. DOI: 10.1109/ASSCC.2015.7387444
    Keywords: CMOS digital integrated circuits;analogue-digital conversion;computerised monitoring;digital readout;temperature sensors;thermal diffusivity;voltage-controlled oscillators;VCO-based phase-domain ADC;VCO-based readout;bulk silicon;digital circuitry;highly digital temperature sensor;microprocessors;size 160 nm;standard CMOS process;systems-on-chip;temperature -35 degC to 125 degC;temperature-dependent thermal diffusivity;thermal monitoring;CMOS integrated circuits;CMOS process;Heating;Radiation detectors;Temperature measurement;Temperature sensors.
    Abstract: ...
    A highly digital temperature sensor based on the temperature-dependent thermal diffusivity of bulk silicon has been realized in a standard 160-nm CMOS process. The sensor achieves an inaccuracy of 2.9C (3a) from -35C to 125C with no trimming and 1.2C (3a) after a single-point trim, while achieving a resolution of 0.47C (rms) at 1 kSa/s. Its compact area (2800 m2) is enabled by the adoption of a VCO-based phase-domain ADC. Since 53% of the sensor area is occupied by digital circuitry, the sensor can be easily ported to more advanced CMOS technologies with further area reduction, which makes it well suited for thermal monitoring in microprocessors and other systems-on-chip.

  36. A 25mW Smart CMOS Wind Sensor with Corner Heaters
    Wouter Brevet; Fabio Sebastiano; Kofi A.A. Makinwa;
    In 41st Annual Conference of IEEE Industrial Electronics Society,
    Yokohama, Japan, pp. 001194-001199, Nov 2015. DOI: 10.1109/IECON.2015.7392262
    Keywords: CMOS integrated circuits;heating;intelligent sensors;wind power;wires (electric);corner heater;logic on-chip;power 25 mW;sensor bitstream output off-chip decimation;sensor chip thermal design;size 0.7 mum;smart CMOS thermal wind sensor;standard CMOS process;Clocks;Frequency modulation;Heating;Thermal sensors;Wind speed;Electrothermal filter (ETF);Smart wind sensor;Thermal sensors;thermal sigma-delta modulatiom.
    Abstract: ...
    A smart CMOS thermal wind sensor has been optimized for commercial use. Optimizing the sensor chip's thermal design resulted in better area efficiency and improved thermal dynamics with respect to prior work. The latter simplifies the off-chip decimation of the sensor's bitstream outputs. Moreover, by realizing more logic on-chip, the number of bond wires has been reduced by 33%, to 8, thus reducing manufacturing costs. Fabricated in a standard 0.7m CMOS process, the sensor chip occupies 44mm2 and consumes 25mW of heating power, while achieving an inaccuracy of 6% (speed) and 2 (direction), for wind speeds between 4 and 25m/s.

  37. Automatic Common-mode Rejection Calibration
    Fabio Sebastiano; Lucien J. Breems; Raf Roovers;
    Patent, Europe 2195922 B1, March 2015.

  38. A/D converter input stage providing high linearity and gain matching between multiple channels
    Robert H.M. van Veldhoven; Fabio Sebastiano;
    Patent, United Sates 9154149 B2, October 2015.

  39. A 0.07mm² 2-Channel Instrumentation Amplifier with 0.1% Gain Matching in 0.16µm CMOS
    Fabio Sebastiano; Federico Butti; Robert H.M. van Veldhoven; Paolo Bruschi;
    In International Solid-state Circuits Conference Digest of Technical Papers,
    San Francisco, CA, pp. 294 - 295, February9--13 2014. DOI: 10.1109/ISSCC.2014.6757440
    Keywords: CMOS integrated circuits;instrumentation amplifiers;2-channel instrumentation amplifier;CMOS;DEM scheme;IA;angular sensors;cosine outputs;cost-constrained automotive applications;dynamic element matching scheme;gain matching;high chopping frequency;multichannel sensor outputs;resistive magnetic sensor;sensor front-ends;sensor operation;size 0.16 mum;voltage 17 muV;Accuracy;CMOS integrated circuits;Gain measurement;Instruments;Noise measurement;Solid state circuits;Switches.
    Abstract: ...
    Extremely small-area sensor front-ends are required for cost-constrained automotive applications. Instrumentation amplifiers (IA) for such front-ends must process multi-channel sensor outputs and provide gain matching over the channels for proper sensor operation. Angular sensors are a typical example, in which the sine and cosine outputs of a resistive magnetic sensor must be processed with adequate gain matching to avoid unacceptable angular errors. This paper presents a 2-channel instrumentation amplifier in 0.16µm CMOS with 0.1% gain matching and occupying 0.035mm2 per channel. This represents a 13.3x area improvement with respect to state-of-the-art designs with similar gain accuracy [1]-[4], while maintaining low noise (18.7nV/√Hz), low offset (17µV) and high power efficiency (NEF=12.9). The accurate gain matching in a limited area is enabled by the adoption of a dynamic element matching (DEM) scheme and by the use of a high chopping frequency.

  40. A 0.008-mm² area-optimized thermal-diffusivity-based temperature sensor in 160-nm CMOS for SoC thermal monitoring
    Ugur Sonmez; Rui Quan; Fabio Sebastiano; Kofi. A. A. Makinwa;
    In Proc. European Solid-State Circuits Conference,
    Venice, Italy, pp. 395-398, September22--26 2014. DOI: 10.1109/ESSCIRC.2014.6942105
    Keywords: CMOS integrated circuits;system-on-chip;temperature measurement;temperature sensors;thermal diffusivity;SoC thermal monitoring;area-optimized thermal-diffusivity-based temperature sensor;bulk silicon;microprocessors;size 160 nm;standard CMOS process;systems-on-chip;temperature-dependent thermal diffusivity;thermal monitoring;Accuracy;Heating;System-on-chip;Temperature measurement;Temperature sensors.
    Abstract: ...
    An array of temperature sensors based on the temperature-dependent thermal diffusivity of bulk silicon has been realized in a standard 160-nm CMOS process. The sensors achieve an inaccuracy of ±2.4 °C (3σ) from -40 to 125 °C with no trimming and ±0.65 °C (3σ) with a one temperature trim. Each sensor occupies 0.008 mm², and achieves a resolution of 0.21 °C (rms) at 1 kSa/s. This combination of accuracy, speed, and small size makes such sensors well suited for thermal monitoring in microprocessors and other systems-on-chip.

  41. Magnetic sensor arrangement
    Fabio Sebastiano; Robert H.M. van Veldhoven;
    Patent, Europe 2672285, May 2014.

  42. Modulator with high signal to noise ratio
    Fabio Sebastiano; Robert H.M. van Veldhoven; Selcuk Ersoy;
    Patent, Europe 14160161, March 2014.

  43. Driver for switched-capacitor circuits
    Fabio Sebastiano;
    Patent, Europe 14175054.7, June 2014.

  44. Mobility-based Time References for Wireless Sensor Networks
    Fabio Sebastiano; Lucien J. Breems; Kofi A.A. Makinwa;
    Springer, , 2013.
    Abstract: ...
    This book describes the use of low-power low-cost and extremely small radios to provide essential time reference for wireless sensor networks. The authors explain how to integrate such radios in a standard CMOS process to reduce both cost and size, while focusing on the challenge of designing a fully integrated time reference for such radios. To enable the integration of the time reference, system techniques are proposed and analyzed, several kinds of integrated time references are reviewed, and mobility-based references are identified as viable candidates to provide the required accuracy at low-power consumption. Practical implementations of a mobility-based oscillator and a temperature sensor are also presented, which demonstrate the required accuracy over a wide temperature range, while drawing 51-µW from a 1.2-V supply in a 65-nm CMOS process.

  45. A 0.25mm² AC-Biased MEMS Microphone Interface with 58dBA SNR
    Sel\c{c}uk Ersoy; Robert H.M. van Veldhoven; Fabio Sebastiano; Klaus Reimann;
    In International Solid-state Circuits Conference Digest of Technical Papers,
    San Francisco, CA, pp. 382-383, February17--21 2013. DOI: 10.1109/ISSCC.2013.6487779
    Keywords: AC machines;DC machines;capacitance;electronics packaging;micromechanical devices;microphones;AC-biased MEMS microphone interface;AC-biasing scheme;ASIC size reduction;DC-biased microphone;SNR;capacitive MEMS microphone roadmap;module packaging cost;noise.
    Abstract: ...
    Capacitive MEMS microphone roadmaps are mainly driven by increasing SNR and reducing size/cost. This requires smaller microphones, ASICs with lower noise and smaller area, and cheaper packaging. Because of fundamental limitations, traditional DC-biased microphones will have difficulty following these trends. This paper proposes an AC-biasing scheme, which leads to a significant reduction in ASIC size and module packaging cost.

  46. A 0.1-mm² 3-Channel Area-Optimized ΣΔ ADC in 0.16-µm CMOS with 20-kHz BW and 86-dB DR
    Fabio Sebastiano; Robert H.M. van Veldhoven;
    In Proc. European Solid-State Circuits Conference,
    Bucharest, Romania, pp. 375 - 378, September16--20 2013. DOI: 10.1109/ESSCIRC.2013.6649151
    Keywords: CMOS integrated circuits;analogue-digital conversion;automotive electronics;delta-sigma modulation;3-channel area-optimized S? ADC;CMOS;automotive sensors;capacitors;channel latency;channel multiplexing;frequency 20 kHz;frequency 75 MHz;front-ends;inter-channel gain mismatch;oversampling ratio;size 0.16 mum;Capacitors;Crosstalk;Gain;Modulation;Multiplexing;Noise;Sensors.
    Abstract: ...
    Front-ends for automotive sensors must digitize multiple channels with high resolution while minimizing their silicon area to save costs. Both channel latency and inter-channel gain mismatch must be minimized to be able to serve multiple sensor applications, ranging from ABS to power steering, with the same front-end. The proposed S? ADC simultaneously digitizes 3 channels, each with a DR of 86 dB over a 20-kHz BW using a 75-MHz clock. Channel latency is <40 ns and inter-channel gain mismatch is <0.2%. The ADC occupies only 0.1 mm² in a 0.16-µm CMOS process. The small area is enabled by channel multiplexing, allowing component sharing among the channels, and by the large oversampling ratio (OSR), allowing for smaller capacitors.

  47. Method and system for impulse radio wakeup
    Fabio Sebastiano; Salvatore Drago; Lucien J. Breems; Domine M.W. Leenaerts;
    Patent, United States 8620394 B2, December 2013.

  48. Magnetic sensor with low electric offset
    Fabio Sebastiano; Robert H.M. van Veldhoven;
    Patent, Europe 2562556 A2, February 2013.

  49. Magnetic sensor with low electric offset
    Fabio Sebastiano; Robert H.M. van Veldhoven;
    Patent, United States 8664941 B2, March 2013.

  50. Magnetic sensor with low electric offset
    Fabio Sebastiano; Robert H.M. van Veldhoven;
    Patent, China 102954808 A, March 2013.

  51. Magnetic sensor arrangement
    Fabio Sebastiano; Robert H.M. van Veldhoven;
    Patent, United States 0328550 A1, December 2013.

  52. Offset compensation for zero-crossing detection
    Robert H.M. van Veldhoven; Fabio Sebastiano;
    Patent, Europe 14160161, October 2013.

  53. Automatic Common-mode Rejection Calibration
    Fabio Sebastiano; Lucien J. Breems; Raf Roovers;
    Patent, United States 8174416, May 2012.

  54. Frequency synthesiser
    Salvatore Drago; Fabio Sebastiano; Domine M.W. Leenaerts; Lucien J. Breems; Bram Nauta;
    Patent, China 102369665 A, March 2012.

  55. A 65-nm CMOS temperature-compensated mobility-based frequency reference for Wireless Sensor Networks
    Fabio Sebastiano; Lucien J. Breems; Kofi Makinwa; Salvatore Drago; Domine M. W. Leenaerts; Bram Nauta;
    {IEEE} J. Solid-State Circuits,
    Volume 46, Issue 7, pp. 1544 - 1552, July 2011. DOI: 10.1109/JSSC.2011.2143630
    Keywords: CMOS integrated circuits;compensation;electron mobility;wireless sensor networks;MOS transistor;current 42.6 muA;electron mobility;mobility-based frequency reference;size 65 nm;temperature -55 degC to 125 degC;temperature-compensated CMOS frequency reference;two-point trim;voltage 1.2 V;wireless sensor networks;Accuracy;Frequency conversion;Oscillators;Temperature;Temperature measurement;Temperature sensors;Wireless sensor networks;CMOS integrated circuits;Charge carrier mobility;MOSFET;crystal-less clock;frequency reference;low voltage;sigma-delta modulation;smart sensors;temperature compensation;temperature sensors;ultra-low power;wireless sensor networks.
    Abstract: ...
    A temperature-compensated CMOS frequency reference based on the electron mobility in a MOS transistor is presented. Over the temperature range from -55 °C to 125 °C, the frequency spread of the complete reference is less than ±0.5% after a two-point trim and less than ±2.7% after a one-point trim. These results make it suitable for use in Wireless Sensor Network nodes. Fabricated in a baseline 65-nm CMOS process, the 150 kHz frequency reference occupies 0.2 mm² and draws 42.6 µA from a 1.2-V supply at room temperature.

  56. A 1.8 µW 60 nV/√Hz Capacitively-Coupled Chopper Instrumentation Amplifier in 65 nm CMOS for Wireless Sensor Nodes
    Qinwen Fan; Fabio Sebastiano; Johan H. Huijsing; Kofi A.A. Makinwa;
    {IEEE} J. Solid-State Circuits,
    Volume 46, Issue 7, pp. 1534 - 1543, July 2011. DOI: 10.1109/JSSC.2011.2143610
    Keywords: CMOS integrated circuits;choppers (circuits);instrumentation amplifiers;wireless sensor networks;CMOS technology;CMRR;DC servo loop;PSRR;biopotential sensing;capacitively-coupled chopper instrumentation amplifier;chopping ripple;current 1.8 muA;electrode offset suppression;low-power precision instrumentation amplifier;noise efficiency factor;positive feedback loop;power 1.8 muW;rail-to-rail input common-mode range;ripple reduction loop;size 65 nm;voltage 1 V;wireless sensor nodes;Capacitors;Choppers;Impedance;Noise;Sensors;Topology;Wireless sensor networks;Bio-signal sensing;chopping;high power efficiency;low offset;low power;precision amplifier;wireless sensor nodes.
    Abstract: ...
    This paper presents a low-power precision instrumentation amplifier intended for use in wireless sensor nodes. It employs a capacitively-coupled chopper topology to achieve a rail-to-rail input common-mode range as well as high power efficiency. A positive feedback loop is employed to boost its input impedance, while a ripple reduction loop suppresses the chopping ripple. To facilitate bio-potential sensing, an optional DC servo loop may be employed to suppress electrode offset. The IA achieves 1 µV offset, 0.16% gain inaccuracy, 134 dB CMRR, 120 dB PSRR and a noise efficiency factor of 3.3. The instrumentation amplifier was implemented in a 65 nm CMOS technology. It occupies only 0.1 mm² chip area (0.2 mm² with the DC servo loop) and consumes 1.8 µA current (2.1 µA with the DC servo loop) from a 1 V supply.

  57. Effects of Packaging and Process Spread on a Mobility-Based Frequency Reference in 0.16-µm CMOS
    Fabio Sebastiano; Lucien J. Breems; Kofi Makinwa; Salvatore Drago; Domine M. W. Leenaerts; Bram Nauta;
    In Proc. European Solid-State Circuits Conference,
    Helsinki, Finland, pp. 511 - 514, September12-16 2011. DOI: 10.1109/ESSCIRC.2011.6044934
    Keywords: CMOS integrated circuits;MOSFET;ceramic packaging;electron mobility;low-power electronics;plastic packaging;reference circuits;wireless sensor networks;CMOS process;ceramic packages;electron mobility;frequency 50 kHz;low-voltage low-power circuit;mobility-based frequency reference;off-chip components;packaging;plastic packages;process spread;size 0.16 mum;temperature -55 degC to 125 degC;temperature 293 K to 298 K;thick-oxide MOS transistors;thin-oxide MOS transistors;voltage 1.2 V;wireless sensor networks;Accuracy;Ceramics;Oscillators;Plastics;Temperature distribution;Temperature measurement;Transistors.
    Abstract: ...
    In this paper, we explore the robustness of frequency references based on the electron mobility in a MOS transistor by implementing them with both thin-oxide and thick-oxide MOS transistors in a 0.16-µm CMOS process, and by testing samples packaged in both ceramic and plastic packages. The proposed low-voltage low-power circuit requires no off-chip components, making it suitable for applications requiring fully integrated solutions, such as Wireless Sensor Networks. Over the temperature range from -55 °C to 125 °C, its frequency spread is less than ±1% (3σ) after a one-point trim. Fabricated in a baseline 0.16-µm CMOS process, the 50 kHz frequency reference occupies 0.06 mm² and, at room temperature, its consumption with a 1.2-V supply is less than 17 µW.

  58. A 200 µA Duty-Cycled PLL for Wireless Sensor Nodes in 65 nm CMOS
    Salvatore Drago; Domine M.W. Leenaerts; Bram Nauta; Fabio Sebastiano; Kofi A.A. Makinwa; Lucien J. Breems;
    {IEEE} J. Solid-State Circuits,
    Volume 45, Issue 7, pp. 1305 - 1315, July 2010. DOI: 10.1109/JSSC.2010.2049458
    Keywords: CMOS integrated circuits;UHF integrated circuits;frequency synthesizers;low-power electronics;phase locked loops;wireless sensor networks;CMOS technology;DCPLL circuit;current 200 muA;duty-cycled PLL;frequency 300 MHz to 1.2 GHz;frequency error;low-power high-frequency synthesizer;size 65 nm;voltage 1.3 V;wireless sensor networks;wireless sensor nodes;Batteries;CMOS technology;Energy consumption;Frequency synthesizers;Integrated circuit technology;Jitter;Oscillators;Phase locked loops;Phase noise;Wireless sensor networks;CMOS;PLL;WSN;duty-cycle;frequency stability;frequency synthesizer;fully integrated;ultra-low-power;wireless sensor networks.
    Abstract: ...
    The design of a duty-cycled PLL (DCPLL) capable of burst mode operation is presented. The proposed DCPLL is a moderately accurate low-power high-frequency synthesizer suitable for use in nodes for wireless sensor networks (WSN). Thanks to a dual loop configuration, the PLL's total frequency error, once in lock, is less than 0.25% from 300 MHz to 1.2 GHz. It employs a fast start-up DCO which enables its operation at duty-cycles as low as 10%. Fabricated in a baseline 65 nm CMOS technology, the DCPLL circuit occupies 0.19 x 0.15 mm² and draws 200 µA from a 1.3 V supply when generating bursts of 1 GHz signal with a 10% duty-cycle.

  59. A 1.2-V 10-µW NPN-Based Temperature Sensor in 65-nm CMOS With an Inaccuracy of 0.2 °C (3σ) From -70 °C to 125 °C
    Fabio Sebastiano; Lucien J. Breems; Kofi Makinwa; Salvatore Drago; Domine M. W. Leenaerts; Bram Nauta;
    {IEEE} J. Solid-State Circuits,
    Volume 45, Issue 12, pp. 2591 - 2601, December 2010. DOI: 10.1109/JSSC.2010.2076610
    Keywords: CMOS integrated circuits;correlation methods;signal sampling;temperature sensors;CMOS;correlated double sampling;dynamic element matching;npn transistor;power 10 muW;size 65 nm;temperature -70 C to 125 C;temperature sensor;voltage 1.2 V;CMOS analog integrated circuits;CMOS process;Intelligent sensors;Sigma delta modulation;Temperature sensors;CMOS analog integrated circuits;sigma-delta modulation;smart sensors;temperature sensors.
    Abstract: ...
    An NPN-based temperature sensor with digital output has been realized in a 65-nm CMOS process. It achieves a batch-calibrated inaccuracy of (3σ) and a trimmed inaccuracy of (3σ) over the temperature range from -70 °C to 125 °C. This performance is obtained by the use of NPN transistors as sensing elements, the use of dynamic techniques, i.e., correlated double sampling and dynamic element matching, and a single room-temperature trim. The sensor draws 8.3 µA from a 1.2-V supply and occupies an area of 0.1 mm².

  60. A 1.2V 10µW NPN-based temperature sensor in 65nm CMOS with an inaccuracy of ±0.2°C (3σ) from -70°C to 125°C
    Fabio Sebastiano; Lucien J. Breems; Kofi Makinwa; Salvatore Drago; Domine M. W. Leenaerts; Bram Nauta;
    In International Solid-state Circuits Conference Digest of Technical Papers,
    San Francisco, CA, pp. 312 - 313, February7--11 2010. DOI: 10.1109/ISSCC.2010.5433895
    Keywords: CMOS integrated circuits;signal processing equipment;temperature sensors;CMOS technology;batch calibrated inaccuracy;current 8.3 A;power 10 W;size 65 nm;temperature -70 C to 125 C;temperature sensor;voltage 1.2 V;CMOS technology;Pipelines;Robustness;Sampling methods;Switches;Tail;Temperature sensors;Testing;Timing;Voltage.
    Abstract: ...
    A temperature sensor utilizing NPN transistors has been realized in a 65 nm CMOS process. It achieves a batch-calibrated inaccuracy of ±0.5°C (3σ) and a trimmed inaccuracy of ±0.2°C (3σ) from -70°C to 125°C The sensor draws 8.3 µA from a 1.2 V supply and occupies an area of 0.1 mm².

  61. A 2.4GHz 830pJ/bit duty-cycled wake-up receiver with -82dBm sensitivity for crystal-less wireless sensor nodes
    Salvatore Drago; Domine M.W. Leenaerts; Fabio Sebastiano; and Lucien J. Breems; Kofi A.A. Makinwa; Bram Nauta;
    In International Solid-state Circuits Conference Digest of Technical Papers,
    San Francisco, CA, pp. 224 - 225, February7--11 2010. DOI: 10.1109/ISSCC.2010.5433955
    Keywords: CMOS integrated circuits;UHF integrated circuits;field effect MMIC;radio receivers;ultra wideband communication;wireless sensor networks;CMOS wake up receiver;bit rate 500 kbit/s;broadband IF heterodyne architecture;crystal less wireless sensor nodes;frequency 2.4 GHz;impulse radio modulation;non coherent energy detection;power 415 muW;size 65 nm;Baseband;Bit error rate;Clocks;Filters;Gain measurement;Pulse amplifiers;Radio frequency;Radiofrequency amplifiers;Voltage;Wireless sensor networks.
    Abstract: ...
    A 65 nm CMOS 2.4 GHz wake-up receiver operating with low-accuracy frequency references has been realized. Robustness to frequency inaccuracy is achieved by employing non-coherent energy detection, broadband-IF heterodyne architecture and impulse-radio modulation. The radio dissipates 415 µW at 500 kb/s and achieves a sensitivity of -82 dBm with an energy efficiency of 830 pJ/bit.

  62. A 65-nm CMOS temperature-compensated mobility-based frequency reference for Wireless Sensor Networks
    Fabio Sebastiano; Lucien J. Breems; Kofi Makinwa; Salvatore Drago; Domine M. W. Leenaerts; Bram Nauta;
    In Proc. European Solid-State Circuits Conference,
    Sevilla, Spain, pp. 102 - 105, September14--16 2010. DOI: 10.1109/ESSCIRC.2010.5619792
    Keywords: CMOS integrated circuits;MOSFET;electron mobility;wireless sensor networks;CMOS temperature-compensated mobility;MOS transistor;current 42.6 muA;electron mobility;frequency 150 kHz;frequency reference;size 65 nm;temperature -55 C to 125 C;voltage 1.2 V;wireless sensor network;Accuracy;CMOS integrated circuits;Calibration;Oscillators;Temperature measurement;Temperature sensors;Wireless sensor networks.
    Abstract: ...
    For the first time, a temperature-compensated CMOS frequency reference based on the electron mobility in a MOS transistor is presented. Over the temperature range from -55 °C to 125 °C, its frequency spread is less than ±0.5% after a two-point trim and less than ±2.7% after a one-point trim. These results make it suitable for use in Wireless Sensor Network nodes. Fabricated in a baseline 65-nm CMOS process, the 150 kHz frequency reference occupies 0.2 mm² and draws 42.6 µA from a 1.2-V supply at room temperature.

  63. A 1.8µW 1-µV-offset capacitively-coupled chopper instrumentation amplifier in 65nm CMOS
    Qinwen Fan; Fabio Sebastiano; Johan H. Huijsing; Kofi A.A. Makinwa;
    In Proc. European Solid-State Circuits Conference,
    Sevilla, Spain, pp. 170 - 173, September14--16 2010. DOI: 10.1109/ESSCIRC.2010.5619902
    Keywords: CMOS integrated circuits;instrumentation amplifiers;CMOS;input impedance;noise efficiency factor;positive feedback loop;precision capacitively-coupled chopper instrumentation amplifier;rail-to-rail DC common-mode input range;ripple reduction loop;size 65 nm;Accuracy;Choppers;Impedance;Instruments;Noise;Resistors;Topology.
    Abstract: ...
    This paper describes a precision capacitively-coupled chopper instrumentation amplifier (CCIA). It achieves 1µV offset, 134dB CMRR, 120dB PSRR, 0.16% gain accuracy and a noise efficiency factor (NEF) of 3.1, which is more than 3x better than state-of-the-art. It has a rail-to-rail DC common-mode (CM) input range. Furthermore, a positive feedback loop (PFL) is used to boost the input impedance, and a ripple reduction loop (RRL) is used to reduce the ripple associated with chopping. The CCIA occupies only 0.1mm² in a 65nm CMOS technology. It can operate from a 1V supply, from which it draws only 1.8µA.

  64. A 2.1 µW Area-Efficient Capacitively-Coupled Chopper Instrumentation Amplifier for ECG Applications in 65 nm CMOS
    Qinwen Fan; Fabio Sebastiano; Johan H. Huijsing; Kofi A.A. Makinwa;
    In Proc. Asian Solid-State Circuits Conference,
    Beijing, China, pp. 1 - 4, November8--10 2010. DOI: 10.1109/ASSCC.2010.5716624
    Keywords: CMOS integrated circuits;amplifiers;biomedical electrodes;choppers (circuits);electrocardiography;CMOS technology;DC servo loop;ECG application;area efficient chopper instrumentation amplifier;capacitive feedback network;capacitively coupled chopper instrumentation amplifier;electrocardiography;electrode-tissue interface;power 2.1 muW;switched capacitor integrator;Choppers;DSL;Earth Observing System;Electrocardiography;Impedance;Instruments;Noise.
    Abstract: ...
    This paper describes a capacitively-coupled chopper instrumentation amplifier for use in electrocardiography (ECG). The amplifier's gain is accurately defined by a capacitive feedback network, while a DC servo loop rejects the DC offset generated by the electrode-tissue interface. The high-pass corner frequency established by the servo loop is realized by an area-efficient switched-capacitor integrator. Additional feedback loops are employed to boost the amplifier's input-impedance to 80 MΩ and to suppress the chopper ripple. Implemented in a 65 nm CMOS technology, the amplifier draws 2.1 µA from a 1 V supply and occupies 0.2 mm².

  65. Automatic Common-mode Rejection Calibration
    Fabio Sebastiano; Lucien J. Breems; Raf Roovers;
    Patent, China 101809863 A, August 2010.

  66. Method and system for impulse radio wakeup
    Fabio Sebastiano; Salvatore Drago; Lucien J. Breems; Domine M.W. Leenaerts;
    Patent, Europe 2206240 A2, July 2010.

  67. Method and system for impulse radio wakeup
    Fabio Sebastiano; Salvatore Drago; Lucien J. Breems; Domine M.W. Leenaerts;
    Patent, China 101816130 A, August 2010.

  68. Frequency synthesiser
    Salvatore Drago; Fabio Sebastiano; Domine M.W. Leenaerts; Lucien J. Breems; Bram Nauta;
    Patent, World 113108 A1, October 2010.

  69. Frequency synthesiser
    Salvatore Drago; Fabio Sebastiano; Domine M.W. Leenaerts; Lucien J. Breems; Bram Nauta;
    Patent, Europe 2237418 A2, October 2010.

  70. Impulse-Based Scheme for Crystal-Less ULP Radios
    Salvatore Drago; Fabio Sebastiano; Lucien J. Breems; Domine M.W. Leenaerts; Kofi A.A. Makinwa; Bram Nauta;
    {IEEE} Trans. Circuits Syst. {I},
    Volume 56, Issue 5, pp. 1041 - 1052, May 2009. DOI: 10.1109/TCSI.2009.2015208
    Keywords: access protocols;ad hoc networks;clocks;low-power electronics;modulation;ultra wideband communication;wireless sensor networks;ad hoc modulation;crystal-less ULP radio;crystal-less clock generator;duty-cycled wake-up radio;frequency 17.7 MHz;frequency 2.4 GHz;impulse radio;medium access control protocol;power 100 muW;ultra-low-power radio;wireless sensor network;Crystal-less clock;EDICS Category: COMM110A5, COMM200, COMM250A5;impulse radio;ultra-low power (ULP);wake-up radio;wireless sensor network (WSN).
    Abstract: ...
    This study describes a method of implementing a fully integrated ultra-low-power (ULP) radio for wireless sensor networks (WSNs). This is achieved using an ad hoc modulation scheme (impulse radio), with a bandwidth of 17.7 MHz in the 2.4 GHz-ISM band and a specific medium access control (MAC) protocol, based on a duty-cycled wake-up radio and a crystal-less clock generator. It is shown that the total average power consumption is expected to be less than 100 µW with a clock generator inaccuracy of only 1%.

  71. A Low-Voltage Mobility-Based Frequency Reference for Crystal-Less ULP Radios
    Fabio Sebastiano; Lucien J. Breems; Kofi A.A. Makinwa; Salvatore Drago; Domine M.W. Leenaerts; Bram Nauta;
    {IEEE} J. Solid-State Circuits,
    Volume 44, Issue 7, pp. 2002 -2009, July 2009. DOI: 10.1109/JSSC.2009.2020247
    Keywords: CMOS integrated circuits;MOSFET;wireless sensor networks;CMOS technology;MOS transistor;crystal-less ULP radios;current 34 muA;electron mobility;frequency 100 kHz;low-voltage low-power circuit;low-voltage mobility-based frequency reference;size 65 nm;temperature -22 degC to 85 degC;temperature 293 K to 298 K;voltage 1.2 V;wireless sensor networks;CMOS technology;Circuits;Electron mobility;Energy consumption;Frequency synchronization;MOSFETs;Oscillators;Silicon;Temperature sensors;Wireless sensor networks;CMOS analog integrated circuits;Charge carrier mobility;crystal-less clock;low voltage;relaxation oscillators;ultra-low power;wireless sensor networks.
    Abstract: ...
    The design of a 100 kHz frequency reference based on the electron mobility in a MOS transistor is presented. The proposed low-voltage low-power circuit requires no off-chip components, making it suitable for application in wireless sensor networks (WSN). After a single-point calibration, the spread of its output frequency is less than 1.1% (3σ) over the temperature range from -22 °C to 85 °C . Fabricated in a baseline 65 nm CMOS technology, the frequency reference circuit occupies 0.11 mm² and draws 34 µA from a 1.2 V supply at room temperature.

  72. A 200 µA duty-cycled PLL for wireless sensor nodes
    Salvatore Drago; Domine M.W. Leenaerts; Bram Nauta; Fabio Sebastiano; Kofi A.A. Makinwa; Lucien J. Breems;
    In Proc. European Solid-State Circuits Conference,
    Athens, Greece, pp. 132 - 135, September14--18 2009. DOI: 10.1109/ESSCIRC.2009.5325979
    Keywords: CMOS integrated circuits;UHF detectors;detector circuits;frequency synthesizers;low-power electronics;phase locked loops;wireless sensor networks;CMOS process;burst mode;current 200 muA;duty cycled PLL;frequency 1 GHz;low power frequency synthesizer;size 0.15 mm;size 0.19 mm;size 65 nm;voltage 1.3 V;wireless sensor nodes;Phase locked loops;Wireless sensor networks.
    Abstract: ...
    A duty-cycled PLL operating in burst mode is presented. It is an essential building block of a moderately accurate low-power frequency synthesizer suitable for use in nodes for wireless sensor networks. Once in lock, the PLL's frequency error is less than 0.1% (rms). Fabricated in a baseline 65 nm CMOS process, the PLL occupies 0.19 times 0.15 mm² and draws 200 µA from a 1.3-V supply when generating a 1 GHz signal with a duty cycle of 10%.

  73. Automatic Common-mode Rejection Calibration
    Fabio Sebastiano; Lucien J. Breems; Raf Roovers;
    Patent, World 040697 A3, August 2009.

  74. Power saving method and system for wireless communications device
    Salvatore Drago; Fabio Sebastiano; Domine M.W. Leenaerts; Lucien J. Breems;
    Patent, World 044368 A2, April 2009.

  75. Method and system for impulse radio wakeup
    Fabio Sebastiano; Salvatore Drago; Lucien J. Breems; Domine M.W. Leenaerts;
    Patent, World 044365 A3, June 2009.

  76. Impulse Based Scheme for Crystal-less ULP Radios
    Fabio Sebastiano; Salvatore Drago; Lucien J. Breems; Domine M.W. Leenaerts; Kofi A.A. Makinwa; Bram Nauta;
    In Proc. IEEE International Symposium on Circuits and Systems,
    pp. 1508 - 1511, May18--21 2008. DOI: 10.1109/TCSI.2009.2015208
    Keywords: access protocols;ad hoc networks;clocks;low-power electronics;modulation;ultra wideband communication;wireless sensor networks;ad hoc modulation;crystal-less ULP radio;crystal-less clock generator;duty-cycled wake-up radio;frequency 17.7 MHz;frequency 2.4 GHz;impulse radio;medium access control protocol;power 100 muW;ultra-low-power radio;wireless sensor network;Crystal-less clock;EDICS Category: COMM110A5, COMM200, COMM250A5;impulse radio;ultra-low power (ULP);wake-up radio;wireless sensor network (WSN).
    Abstract: ...
    This study describes a method of implementing a fully integrated ultra-low-power (ULP) radio for wireless sensor networks (WSNs). This is achieved using an ad hoc modulation scheme (impulse radio), with a bandwidth of 17.7 MHz in the 2.4 GHz-ISM band and a specific medium access control (MAC) protocol, based on a duty-cycled wake-up radio and a crystal-less clock generator. It is shown that the total average power consumption is expected to be less than 100 µW with a clock generator inaccuracy of only 1%.

  77. A Low-Voltage Mobility-Based Frequency Reference for Crystal-Less ULP Radios
    Fabio Sebastiano; Lucien J. Breems; Kofi A.A. Makinwa; Salvatore Drago; Domine M.W. Leenaerts; Bram Nauta;
    In Proc. European Solid-State Circuits Conference,
    Edinburgh, UK, pp. 306 - 309, September15--19 2008. DOI: 10.1109/ESSCIRC.2008.4681853
    Keywords: CMOS integrated circuits;MOSFET circuits;electron mobility;integrated circuit design;low-power electronics;mobile radio;wireless sensor networks;MOS transistor;crystal less ULP radios;electron mobility;frequency 100 kHz;low voltage mobility based frequency reference;off-chip components;one point calibration;size 65 nm;temperature -22 degC to 85 degC;voltage 1.2 V;wireless sensor networks;CMOS technology;Calibration;Circuits;Energy consumption;Frequency;Oscillators;Silicon;Temperature distribution;Temperature sensors;Wireless sensor networks.
    Abstract: ...
    The design of a 100 kHz frequency reference based on the electron mobility in a MOS transistor is presented. The proposed low-voltage low-power circuit requires no off-chip components, making it suitable for Wireless Sensor Networks (WSN) applications. After one-point calibration the spread of its output frequency is less than 1.1% (3σ) over the temperature range from -22 °C to 85 °C. Fabricated in a baseline 65-nm CMOS technology, the frequency reference occupies 0.11 mm² and draws 34 µA from a 1.2-V supply at room temperature.

  78. On the Temperature Compensation of a Frequency Reference for Crystal-Less ULP Wireless Sensor Networks
    Fabio Sebastiano; Lucien J. Breems; Kofi A.A. Makinwa; Salvatore Drago; Domine M.W. Leenaerts; Bram Nauta;
    In Proc. ProRISC,
    Veldhoven, The Netherlands, pp. 306 - 309, September27--18 2008.
    Abstract: ...
    Each node in a Wireless Sensor Network (WSN) must be provided with a frequency reference to enable network synchronization and RF communication. As the nodes need to be small, cheap and energy efcient, a frequency reference suitable for WSN must show low power consumption and require no off-chip components. A reference based on electron mobility in a MOS transistor demonstrates such features. Its output frequency follows the temperature dependence of mobility, which, although large, is well dened and can be compensated for. It is shown that a temperature sensor with accuracy of only 0.6 °C can be employed for the temperature compensation and that the inaccuracy of a compensated mobility-based frequency reference due to temperature, process spread, voltage supply variations and noise can be as low as 1% on a wide temperature range, fitting radio architectures for WSN applications.

  79. CMOS Transconductors With Nearly Constant Input Ranges Over Wide Tuning Intervals
    Paolo Bruschi; Fabio Sebastiano; Nicol Nizza;
    {IEEE} Trans. Circuits Syst. {II},
    Volume 53, Issue 10, pp. 1002 - 1006, October 2006. DOI: 10.1109/TCSII.2006.882126
    Keywords: CMOS integrated circuits;bipolar integrated circuits;circuit tuning;0.35 micron;CMOS transconductors;bipolar-CMOS-DMOS process;common-mode range;differential input range;low-frequency filters;prototype circuit;tuning intervals;Chemical sensors;Circuit optimization;Circuit simulation;Low pass filters;MOSFETs;Mirrors;Optimization methods;Stability;Transconductors;Voltage;CMOS transconductor;constant input range;low-frequency filters.
    Abstract: ...
    Three different bias strategies aimed to reduce the effect of tuning on either the differential input range or the common-mode range of triode-region CMOS transconductors are presented. The method is applied to an original transconductor topology that is optimized to produce ultralow Gm values. A prototype circuit, which was designed with the 0.35-µm bipolar-CMOS-DMOS (BCD6) process of STMicroelectronics, is presented. The effectiveness and limitations of the method are characterized by means of electrical simulations

  80. A fully integrated very low frequency single-ended Gm-C filter based on a novel transconductor
    Monica Schipani; Fabio Sebastiano; Nicol Nizza; Paolo Bruschi;
    In Proc. IEEE Ph.D. Research in Microelectronics and Electronics,
    Otranto, Italy, pp. 25 - 28, June12--15 2006. DOI: 10.1109/RME.2006.1689887
    Keywords: CMOS integrated circuits;low-pass filters;network topology;0.35 micron;1.5 to 15 Hz;60 muW;CMOS transconductor topology;low pass filter;second order fully integrated filter;single-ended Gm-C filter;single-ended filter architectures;Capacitance;Capacitors;Frequency;Low pass filters;MOSFETs;Mechanical sensors;Noise reduction;Temperature sensors;Topology;Transconductors.
    Abstract: ...
    A second order fully integrated low pass filter with cut-off frequency variable in the range 1.5-15 Hz is presented. The filter is based on a recently proposed CMOS transconductor topology combining G m values of the order of a few nS with large input ranges and suitability to single-ended filter architectures. The performances are validated by simulations performed on a prototype designed with the 0.35 µm BCD6 process of STMicroelectronics. In particular, a dynamic range of 70 dB and power dissipation of 60 µW have been obtained with a corner frequency of 1.5 Hz

  81. A tunable CMOS transconductor for ultra-low Gm with wide differential input voltage range
    Paolo Bruschi; Fabio Sebastiano; Nicol Nizza; Massimo Piotto;
    In Proc. European Conference on Circuit Theory and Design,
    Cork, Ireland, pp. III/337 - III/3, August28--September2 2005. DOI: 10.1109/ECCTD.2005.1523129
    Abstract: ...
    A differential input, single ended output transconductor with gm in the range 0.5-5 nS is presented. The circuit uses a source coupled pair operated in triode region. The need of providing a fixed common mode input voltage, which afflicts circuits based on the same principle, is removed by adopting an original topology. The results of simulations based on the 0.35 µm BCD6 process of STMicroelectronics are presented.

BibTeX support